The present invention relates to electrical circuits and, more particularly, to a frequency divider/counter for use in non-modulo power of 2 applications.
In certain electrical applications, particularly in digital electronic circuits, it is often desirable to step down the frequency of a clock signal by the use of a frequency divider in order to use the stepped-down clock to control certain actions. Similarly, it is often desirable to count a given number of signals on a line over time by the use of a counter to trigger additional actions following the passage of that number of signals. While two separate names, frequency divider and counter, are used for the circuitry which performs the above application, the circuitry required to perform these applications is identical. The only difference being that instead of using a clock signal as an input to the circuitry, the line containing the signals to be counted is used as the input.
When the frequency step-down rate or the count is not equal to 2.sup.N, in other words, is a non-modulo power of 2, circuit designers have used complex circuitry to generate the desired output. Not only has the circuitry been complex, but the complexity has also resulted in irregular circuitry layouts. This has particularly been the case where the frequency divider/counter is fabricated within standard CMOS integrated circuits.
Therefore, what is needed is a non-modulo power of 2 frequency divider/counter which utilizes standard CMOS technology and provides for simpler construction and easier layout.